In efforts to improve the performance of dynamic random-access memory (DRAM) over the past decades, great emphasis has been made to increase the density and bandwidth of the DRAM, but the latency of the DRAM has not been greatly improved.
A DRAM cell structure including a single transistor and a single capacitor, herein referred to as 1T1C, was introduced in 1968. The 1T1C cell structure accounts for the majority of today's off-chip DRAMs. The 1T1C cell structure has a high density but requires a destructive read operation to perform a write back to restore a cell charge, thereby increasing the latency to access 1T1C cells.
A DRAM cell structure including three transistors and a single capacitor, herein referred to as 3T1C, was introduced in 1970. The 3T1C cell structure accounts for numerous variants that are popularly used in today's embedded DRAMs (eDRAMs). The 3T1C cell structure has a low density but it does not require a write-back. The non-destructive read operation that does not require a write-back allows a faster read access time and saves approximately 7 ns or 15% of a row cycle time (tRC) compared to the 1T1C cell structure.
Based on a type of a DRAM array, a memory controller uses different timings to control an access to the DRAM array. Different types of DRAM arrays may be used for different applications. For example, an application requiring a high-density can take advantage of the 1T1C cell structure whereas an application that requires a fast performance may use 3T1C memory cells. Integration of dissimilar types of DRAM cells in a single DRAM array may provide a required density while meeting the performance requirement for an application.